`timescale 1ns/1ps

module tb_breath_led();

reg sys_clk = 1'b0;
reg sys_rst_n;
wire [1:0] led;

breath_led#(.CNT_MAX(17'd10_000)) u_breath_led(
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n),
    .led(led)
);

always #10 sys_clk = ~sys_clk;

initial begin
    sys_rst_n <= 1'b0;
    #100
    sys_rst_n <= 1'b1;
end


endmodule